Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
Platforms: Windows, Mac, BSD, Linux
|License: Freeware||Size: 1.16 MB||Download (29): Icarus Verilog Download|
Hardware::Simulator is a Perl extension for Perl Hardware Descriptor Language. SYNOPSIS use Hardware::Simulator; # NewSignal( perl_variable [, initial_value]); # create a signal called $in_clk, give it an initial value of 1 NewSignal(my $in_clk,1); # Repeater ( time_units , code_ref) #...
|License: Freeware||Size: 10.24 KB||Download (74): Hardware::Simulator Download|
Qfsm is a graphical editor for finite state machines written in C++ using Qt the graphical Toolkit from Trolltech. Finite state machines are a model to describe complex objects or systems in terms of the states they may be in. In practice they can used to design integrated circuits or to create...
|License: Freeware||Size: 2.7 MB||Download (91): Qfsm Download|
Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.
|License: Freeware||Size: 153.6 KB||Download (16): sister Download|
Text::EP3::Verilog Perl module contains a verilog extension for the EP3 preprocessor. SYNOPSIS use Text::EP3; use Text::EP3::Verilog; This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and...
|License: Freeware||Size: 6.14 KB||Download (82): Text::EP3::Verilog Download|
Verilog::Netlist::Net is a Net for a Verilog Module. SYNOPSIS use Verilog::Netlist; ... my $net = $module->find_net (signalname); print $net->name; Verilog::Netlist creates a net for every sc_signal declaration in the current module..
|License: Freeware||Size: 122.88 KB||Download (94): Verilog::Netlist::Net Download|
Verilog::CodeGen module is a Verilog code generator. SYNOPSIS use Verilog::CodeGen; mkdir DeviceLibs/Objects/YourDesign, 0755; chdir DeviceLibs/Objects/YourDesign; # if the directory YourDesign exists, the second argument can be omitted # create YourModule.pl in YourDesign...
|License: Freeware||Size: 18.43 KB||Download (80): Verilog::CodeGen Download|
vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
|License: Shareware||Cost: $0.00 USD||Size: 8.43 MB||Download (19): Verilog Tool Framework Download|
Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an...
|License: Freeware||Size: 20.16 MB||Download (17): scicosHDL Download|
FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and...
|License: Demo||Cost: $0.00 USD||Download (89): FIR HDL Writer Download|
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
Platforms: Windows, Mac, Linux
|License: Freeware||Size: 710.93 KB||Download (30): Eclipse Verilog editor Download|
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
Platforms: Windows, Mac, Linux
|License: Freeware||Size: 142.64 KB||Download (27): HDLObf Download|
Verilog-A Implementation of the Mextram Bipolar Transistor Model
Platforms: Windows, Mac, Linux
|License: Freeware||Size: 15.93 KB||Download (27): Mextram in Verilog-A Download|
PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor's Verilog mode and features a fast compile-simulate-display cycle.
Platforms: Mac, BSD, Linux
|License: Freeware||Size: 1.55 MB||Download (27): PVSim Verilog Simulator Download|
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
Platforms: *nix, Perl, BSD Solaris
|License: Freeware||Download (32): VTracer Download|
Complete mixed signal electronic circuit schematic capture and simulation software. Combine schematics, SPICE, VHDL, Verilog & VHDL-AMS in a unified design and simulation environment. Powerful and easy-to-use design wizards kick start your design. Design wizards include: filters, integrators,...
|License: Shareware||Cost: $168.00 USD||Size: 793.16 MB||Download (46): ViaDesigner Download|
This demo consists of a m-file script (fixed_point_atan2_using_cordic.m) and a m-file function (atan2_fixpt.m). The script contains a step-by-step explanation of how a four quadrant arctan can be calculated using a CORDIC (COordinate Rotation DIgital Computer) algorithm. The first part shows the...
|License: Freeware||Size: 10 KB||Download (20): Fixed-Point ATAN2 using CORDIC Download|
This presentation introduces comparing between the hand coding and auto code generation with Simulink HDL.It uses simple communications models to mention merit/demerit.Additionally,The frame synchronization explained by the book was designed with Stateflow.The figure which is in the book and...
|License: Freeware||Size: 10 KB||Download (21): Compare with hand coding and auto code generation of HDL Download|
There is not "built-ib" Simulink block that is HDL Coder compatible negative or positive edge detectors. Attached are 2 subsystems based on basic logic elements, giving you the Simulink HDL Coder compatible edge detection.
|License: Shareware||Cost: $0.00 USD||Size: 10 KB||Download (18): HDL Coder Compatible edge detector Download|
GTKWave is VCD/EVCD/LXT/Synopsis .out format electronic waveform viewer built using the GTK+ toolkit. The project was originally developed by Tony Bybell but development has now passed to the APT group and we hope to extend and improve GTKWave to support new formats and features. Installation...
|License: Shareware||Cost: $0.00 USD||Size: 3.62 MB||Download (16): gtkwave Download|